Ultra-small vertical cavity surface emitting laser (vcsel) and arrays incorporating the same

ABSTRACT

A laser diode includes a semiconductor structure having an n-type layer, an active region, and a p-type layer. One of the n-type and p-type layers includes a lasing aperture thereon having an optical axis oriented perpendicular to a surface of the active region between the n-type and p-type layers. First and second contacts are electrically connected to the n-type and p-type layers, respectively. The first and/or second contacts are smaller than the lasing aperture in at least one dimension. Related arrays and methods of fabrication are also discussed.

CLAIM OF PRIORITY

This application is a continuation of and claims priority from U.S.patent application Ser. No. 15/951,681 filed Apr. 12, 2018, which claimspriority from U.S. Provisional Patent Application No. 62/484,701entitled “LIGHT DETECTION AND RANGING (LIDAR) DEVICES AND METHODS OFFABRICATING THE SAME” filed Apr. 12, 2017, and U.S. Provisional PatentApplication No. 62/613,985 entitled “ULTRA-SMALL VERTICAL CAVITY SURFACEEMITTING LASER (VCSEL) AND ARRAYS INCORPORATING THE SAME” filed Jan. 5,2018, with the United States Patent and Trademark Office, thedisclosures of which are incorporated by reference herein.

FIELD

The present invention relates to semiconductor-based lasers and relateddevices and methods of operation.

BACKGROUND

Many emerging technologies, such as Internet-of-Things (IoT) andautonomous navigation, may involve detection and measurement of distanceto objects in three-dimensional (3D) space. For example, automobilesthat are capable of autonomous driving may require 3D detection andrecognition for basic operation, as well as to meet safety requirements.3D detection and recognition may also be needed for indoor navigation,for example, by industrial or household robots or toys.

Light based 3D measurements may be superior to radar (low angularaccuracy, bulky) or ultra-sound (very low accuracy) in some instances.For example, a light-based 3D sensor system may include a detector (suchas a photodiode or camera) and a light emitting device (such as a lightemitting diode (LED) or laser diode) as light source, which typicallyemits light outside of the visible wavelength range. A vertical cavitysurface emitting laser (VCSEL) is one type of light emitting device thatmay be used in light-based sensors for measurement of distance andvelocity in 3D space. Arrays of VCSELs may allow for power scaling andcan provide very short pulses at higher power density.

SUMMARY

Some embodiments described herein are directed to a laser diode, such asa VCSEL or other surface-emitting laser diode or edge-emitting laserdiode or other semiconductor laser, and arrays incorporating the same.

In some embodiments, the laser diode may be a surface-emitting laserdiode. The laser diode includes a semiconductor structure comprising ann-type layer, an active region (which may comprise at least one quantumwell layer), and a p-type layer. One of the n-type and p-type layerscomprises a lasing aperture thereon having an optical axis orientedperpendicular to a surface of the active region between the n-type andp-type layers. The laser diode further includes first and secondcontacts electrically connected to the n-type and p-type layers,respectively. The first and/or second contacts are smaller than thelasing aperture in at least one dimension (e.g., length, width,diameter).

In some embodiments, the laser diode may be an edge-emitting laserdiode. The laser diode includes an n-type layer, an active region, ap-type layer, and first and second contacts electrically connected tothe n-type and p-type layers, respectively. A lasing aperture has anoptical axis oriented parallel to a surface of the active region betweenthe n-type and p-type layers. The laser diode further includes first andsecond contacts electrically connected to the n-type and p-type layers,respectively. The first and/or second contacts may be smaller than thelasing aperture in at least one dimension (e.g., length, width,diameter).

According to some embodiments, a laser diode includes a semiconductorstructure having an n-type layer, an active region, and a p-type layer.One of the n-type and p-type layers includes a lasing aperture thereonhaving an optical axis oriented perpendicular to a surface of the activeregion between the n-type and p-type layers. First and second contactsare electrically connected to the n-type and p-type layers,respectively. The first and/or second contacts are smaller than thelasing aperture in at least one dimension.

In some embodiments, a contact area of first and/or second contacts maybe smaller than an aperture area of the lasing aperture. For example, aratio of the contact area to the aperture area is between about 0.05 to30, about 0.1 to 20, about 1 to 10, or about 1 to 3.

In some embodiments, the n-type and p-type layers may be first andsecond Bragg reflector layers, respectively, and the laser diode may bea vertical cavity surface emitting laser (VCSEL).

In some embodiments, a lateral conduction layer may include a surfacehaving the semiconductor structure thereon. One of the first and secondcontacts may be on the surface of the lateral conduction layer adjacentthe semiconductor structure.

In some embodiments, the semiconductor structure may include a residualtether portion and/or a relief feature at a periphery thereof.

In some embodiments, the laser diode may be one of a plurality ofdiscrete laser diodes arranged in an array on a surface of a non-nativesubstrate. Electrically conductive thin-film interconnects may extendalong the surface of the non-native substrate and onto the first and/orsecond contacts to electrically connect the laser diode to one or moreof the plurality of laser diodes.

In some embodiments, the laser diode may be free of electricalconnections through the non-native substrate or the surface thereof. Thenon-native substrate (and/or the surface thereof) may be electricallyinsulating, and/or the non-native substrate may be thermally conducting.

In some embodiments, a spacing between the laser diode and at animmediately adjacent laser diodes of the plurality of laser diodes maybe less than about 500 micrometers, less than about 200 micrometers,less than about 150 micrometers, less than about 100 micrometers, orless than about 50 micrometers, but may be greater than about 30micrometers, greater than about 20 micrometers, or greater than about 10micrometers.

In some embodiments, the surface of the non-native substrate may beplanar. In some embodiments, the surface of the non-native substrate maybe curved. In some embodiments, the non-native substrate may include aflexible material that is bent to define a radius of curvature of thecurved surface.

In some embodiments, the electrically conductive thin-film interconnectsmay electrically connect a subset of the plurality of laser diodes inseries (or anode-to-cathode), where the subset includes the immediatelyadjacent laser diodes. In some embodiments, the subset of the pluralityof laser diodes that are electrically connected in series (oranode-to-cathode) may define a column (or other subset) of the array.

In some embodiments, a concentration of the plurality of laser diodes atperipheral portions of the array may be less than a concentration of theplurality of laser diodes at a central portion of the array.

In some embodiments, the array may further include a plurality of drivertransistors on a surface of the non-native substrate adjacent theplurality of laser diodes. In some embodiments, the electricallyconductive thin-film interconnects may electrically connect respectivesubsets of the plurality of laser diodes in series with respectivedriver transistors of the plurality of driver transistors. In someembodiments, a distance between the respective driver transistors and aclosest laser diode of the respective subsets may be less than about 2millimeters, less than about 1 millimeter, less than about 500micrometers, less than about 150 micrometers, less than about 100micrometers, or less than about 50 micrometers, but may be greater thanabout 30 micrometers, greater than about 20 micrometers, or greater thanabout 10 micrometers.

In some embodiments, a method of fabricating a laser diode, such as aVCSEL or other surface-emitting or edge-emitting laser diode, isprovided. According to some embodiments, a method of fabricating a laserdiode includes providing a semiconductor structure having an n-typelayer, an active region, and a p-type layer, and providing first andsecond contacts electrically connected to the n-type and p-type layers,respectively. One of the n-type and p-type layers includes a lasingaperture thereon having an optical axis oriented perpendicular to asurface of the active region between the n-type and p-type layers. Firstand second contacts are electrically connected to the n-type and p-typelayers, respectively. The first and/or second contacts are smaller thanthe lasing aperture in at least one dimension. The method may furtherinclude fabricating an array of discrete laser diodes, for example,using micro-transfer printing, electrostatic adhesion, and/or other masstransfer techniques.

In some embodiments, an array of discrete laser diodes (also referred toherein as a laser diode array or laser array) is provided. The array oflaser diodes may include surface-emitting laser diodes and/oredge-emitting laser diodes electrically connected in series and/orparallel by thin-film interconnects on non-native rigid and/or flexiblesubstrates. According to some embodiments, a laser array includes aplurality of laser diodes arranged on a non-native substrate, where eachof the laser diodes includes a semiconductor structure having an n-typelayer, an active region, and a p-type layer, and where one of the n-typeand p-type layers includes a lasing aperture thereon having an opticalaxis oriented perpendicular to a surface of the active region betweenthe n-type and p-type layers. First and second contacts are electricallyconnected to the n-type and p-type layers, respectively, where he firstand/or second contacts are smaller than the lasing aperture in at leastone dimension. The array of laser diodes may further include one or moredriver transistors and/or devices of other types/materials (e.g. powercapacitors, etc.) integrated in the array.

Other devices, apparatus, and/or methods according to some embodimentswill become apparent to one with skill in the art upon review of thefollowing drawings and detailed description. It is intended that allsuch additional embodiments, in addition to any and all combinations ofthe above embodiments, be included within this description, be withinthe scope of the invention, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example light-based 3D sensor systemin accordance with some embodiments described herein.

FIG. 2A is a plan view illustrating an example laser diode with reducedanode and cathode contact dimensions in accordance with some embodimentsdescribed herein.

FIG. 2B is a cross-sectional view of the laser diode of FIG. 2A.

FIG. 2C is a perspective view illustrating an example laser diode inaccordance with some embodiments described herein in comparison to aconventional VCSEL chip.

FIG. 3A is a perspective view illustrating a distributed emitter arrayincluding laser diodes in accordance with some embodiments describedherein.

FIG. 3B is a perspective view illustrating a distributed emitter arrayincluding laser diodes on a curved substrate in accordance with someembodiments described herein.

FIGS. 4A-4F are perspective views illustrating an example fabricationprocess for laser diodes in accordance with some embodiments describedherein.

FIGS. 4A′-4G′ are cross-sectional views illustrating an examplefabrication process for laser diodes in accordance with some embodimentsdescribed herein.

FIGS. 5A-5C are images of VCSEL arrays assembled in accordance with someembodiments described herein.

FIGS. 5D-5E are magnified images illustrating broken tether portions andrelief features of VCSELs in accordance with some embodiments describedherein.

FIG. 6A is a perspective view illustrating an example emitter arrayincluding heterogeneous integration of distributed laser diodes anddistributed driver transistors in accordance with some embodimentsdescribed herein.

FIG. 6B is schematic view illustrating an equivalent circuit diagram forthe distributed emitter array of FIG. 6A.

FIG. 6C is a cross-sectional view of the distributed emitter array takenalong line 6C-6C′ of FIG. 6A.

FIG. 7A is a perspective view illustrating an example LIDAR device inaccordance with some embodiments described herein.

FIG. 7B is an exploded view illustrating example components of the LIDARdevice of FIG. 7A.

FIG. 7C is a perspective view illustrating another example LIDAR devicein accordance with some embodiments described herein.

FIG. 8 is a block diagram illustrating an example system architecturefor a LIDAR device in accordance with some embodiments described herein.

FIG. 9 is a cross-sectional view illustrating an example laser diodearray in accordance with further embodiments described herein.

DETAILED DESCRIPTION

Embodiments described herein may arise from realization that morecompact arrays of light emitters may be advantageous in emergingtechnologies. For example, as shown in FIG. 1, a light-based 3D sensorsystem 100, such as a Light Detection and Ranging (LIDAR) system, mayuse time-of-flight (TOF)-based measurement circuit 110 and a 3D imagereconstruction circuit 150 based on a signal received from an opticaldetector circuit 130 and associated optics 140, with a pulsed lightemitting device array 120 as a light source. The time-of-flightmeasurement circuit 110 may determine the distance d to target T bymeasuring the round trip (“time-of-flight”; ToF) of a laser pulse 109reflected by the target T (where d=(speed of light (c)/2)×ToF), whichmay be used by the 3D image reconstruction circuit 150 to create anaccurate 3D map of surroundings. Some advantages of LIDAR systems mayinclude long range; high accuracy; superior object detection andrecognition; higher resolution; higher sampling density of 3D pointcloud; and effectivity in diverse lighting and/or weather conditions.Applications of LIDAR systems may include ADAS (Advanced DriverAssistance Systems), autonomous vehicles, UAVs (unmanned aerialvehicles), industrial automation, robotics, biometrics, modeling,augmented and virtual reality, 3D mapping, and security. The example ofFIG. 1 illustrates a flash LIDAR system, where the pulsed light emittingdevice array 120 emits light for short durations over a relatively largearea to acquire images, in contrast with some traditional scanning LIDARtechniques (which generate image frames by raster scanning). However, itwill be understood that light emitting device arrays 120 describedherein can be used for implementations of scanning LIDAR as well.

Still referring to FIG. 1, the light emitting device array 120 mayinclude a plurality of electrically connected surface-emitting laserdiodes, such as VCSELs, and may be operated with strong single pulses atlow duty cycle or with pulse trains, typically at wavelengths outside ofthe visible spectrum. Because of sensitivity to background light and thedecrease of the signal with distance, several watts of laser power maybe used to detect a target T at a distance d of up to about 100 metersor more.

However, some conventional VCSELs may have sizes defined by dimensions(e.g., length, width, and/or diameter) of about 150 micrometers (μm) toabout 200 μm, which may impose size and/or density constraints on sensorsystems including an array of VCSELs. This relatively large VCSEL sizemay be dictated for use with conventional pick-and-place machines, aswell as for sufficient contact surface area for wire bond pads toprovide electrical connections to the VCSEL. For example, someconventional solder ball or wire bond technology may require more thanabout 30 μm in length for the bond pad alone, while the tip used to pullthe wire bond may have an accuracy on the order of tens of micrometers.

Some embodiments described herein provide light emitting devices, suchas surface-emitting laser diodes (e.g., VCSELs), having reduceddimensions (e.g., lengths and/or widths of about 30 micrometers (μm) orless) without affecting the device performance (e.g., power output). Forexample, the aperture of the VCSEL die (which is the active region wherethe lasing takes place) may be about 10 μm to about 20 μm in diameter.The die length can be reduced to the aperture diameter plus a fewmicrons by reducing or eliminating wasted (non-active) area, and byretaining a few microns (e.g., about 4 μm to about 6 μm or less) ofcombined chip length for the anode and the cathode contacts. This mayprovide a reduction in dimensions (e.g., length and/or width) by afactor of about 10 or more (e.g., die lengths of about 15 micrometers(μm) to about 20 μm, as compared to some conventional VCELs with dielengths of about 150 μm to about 200 μm). In some embodiments, thesereduced die dimensions may allow for fabrication of emitter arraysincluding a greater density (e.g., thousands) of VCSELs or other laserdiodes.

FIGS. 2A and 2B are plan and cross-sectional views illustrating anexample surface-emitting light emitting device (shown as a verticalcavity surface emitting laser diode (VCSEL) chip or die 200, alsoreferred to herein as a VCSEL 200) in accordance with some embodimentsdescribed herein, which includes anode and cathode contacts 211, 212that are smaller than the lasing aperture 210 in at least one dimension(e.g., length, width, and/or diameter). As shown in FIGS. 2A and 2B, theVCSEL 200 includes an active region 205 with one or more quantum wells203 for generation and emission of coherent light 209. The opticalcavity axis 208 of the VCSEL 200 is oriented along the direction ofcurrent flow (rather than perpendicular to the current flow as in someconventional laser diodes), defining a vertical cavity with a lengthalong the direction of current flow. This cavity length of the activeregion 205 may be short compared with the lateral dimensions of theactive region 205, so that the radiation 209 emerges from the surface ofthe cavity rather than from its edge.

The active region 205 may be sandwiched between distributed Braggreflector (DBR) mirror layers (also referred to herein as Braggreflector layers or Bragg mirrors) 201 and 202 provided on a lateralconduction layer (LCL) 206. The LCL 206 may allow for improvedelectrical and/or optical characteristics (as compared to direct contactto the reflector layer 401) in some embodiments. In some embodiments, asurface of the LCL layer 206 may provide a print interface 215 includingan adhesive layer that improves adhesion with an underlying layer orsubstrate. The adhesive layer may be optically transparent to one ormore wavelength ranges and/or can be refractive-index matched to providedesired optical performance. The reflector layers 201 and 202 at theends of the cavity may be made from alternating high and low refractiveindex layers. For example, the reflector layers 201 and 202 may includealternating layers having thicknesses d1 and d2 with refractive indicesn1 and n2 such that n1 dl+n2 d 2=212, to provide wavelength-selectivereflectance at the emission wavelength λ. This vertical construction mayincrease compatibility with semiconductor manufacturing equipment. Forexample, as VCSELs emit light 209 perpendicular to the active region205, tens of thousands of VCSELs can be processed simultaneously, e.g.,by using standard semiconductor wafer processing steps to define theemission area and electrical terminals of the individual VCSELs from asingle wafer. Although described herein primarily with reference toVCSEL structures, it will be understood that embodiments describedherein are not limited to VCSELs, and the laser diode 200 may includeother types of laser diodes that are configured to emit light 209 alongan optical axis 208 that is oriented perpendicular to a substrate orother surface on which the device 200 is provided. It will also beunderstood that, while described herein primarily with reference tosurface-emitting laser structures, laser diodes and laser diode arraysas described herein are not so limited, and may include edge-emittinglaser structures that are configured to emit light along an optical axisthat is oriented parallel to a substrate or other surface on which thedevice is provided as well, as shown in the example of FIG. 9.

The VCSEL 200 may be formed of materials that are selected to providelight emission at or over a desired wavelength range, which may beoutside of the spectrum of light that is visible to the human eye. Forexample, the VCSEL 200 may be a gallium arsenide (GaAs)-based structurein some embodiments. In particular embodiments, the active region 205may include one or more GaAs-based layers (for example, alternatingInGaAs/GaAs quantum well and barrier layers), and the Bragg mirrors 201and 202 may include GaAs and aluminum gallium arsenide(Al_(x)Ga_((1-x))As). For instance, the lower Bragg mirror 201 may be ann-type structure including alternating layers of n-AlAs/GaAs, while theupper Bragg mirror 202 may be a p-type structure including alternatinglayers of p-AlGaAs/GaAs. Although described by way of example withreference to a GaAs-based VCSEL, it will be understood that materialsand/or material compositions of the layers 201, 202, and/or 205 may betuned and/or otherwise selected to provide light emission at desiredwavelengths, for example, using shorter wavelength (e.g., GaN-based)and/or longer wavelength (e.g., InP-based) emitting materials.

In the example of FIGS. 2A and 2B, the VCSEL 200 includes a lasingaperture 210 having a dimension (illustrated as diameter D) of about 12μm, and first and second electrically conductive contact terminals(illustrated as anode contact 211 and cathode contact 212, also referredto herein as first and second contacts). A first electrically conductivefilm interconnect 213 is provided on the first contact 211, and a secondelectrically conductive film interconnect 213 is provided on the secondcontact 212 to provide electrical connections to the VCSEL 200. FIG. 2Bmore clearly illustrates the anode contact 211 and cathode contact 212in cross section, with the conductive film interconnects 213 thereon.The first and second contacts 211 and 212 may provide contacts tosemiconductor regions of opposite conductivity type (P-type and N-type,respectively). Accordingly, embodiments described herein are configuredfor transfer of electric energy to the VCSEL contacts 211 and 212through thin-film interconnects 213, which may be formed by patterningan electrically conductive film, rather than incorporating wire bonds,ribbons, cables, or leads. The interconnections 213 may be formed afterproviding the VCSEL 200 on a target substrate (e.g., a non-nativesubstrate that is different from a source substrate on which the VCSEL200 is formed), for example, using conventional photolithographytechniques, and may be constructed to have low resistance. In thisregard, materials for the electrically conductive film interconnects 213may include aluminum or aluminum alloys, gold, copper, or other metalsformed to a thickness of approximately 200 nm to approximately 500 nm.

As shown in FIG. 2A, the first and second conductive contacts 211 and212 are smaller than the aperture 210 in one or more dimensions. In someembodiments, allowing about 2 μm to about 3 μm for the dimensions ofeach of the contacts 211, 212, the overall dimensions of the VCSEL die200 can be significantly reduced. For example, for anode and cathodecontacts that are 2 μm in length each, a dimension L can be reduced toabout 16 μm (2 μm anode length+12 μm aperture+2 μm cathode length; allmeasured along dimension L) providing a 16×16 μm² die. As anotherexample, for anode and cathode contacts that are 3 μm in length each, adimension L can be reduced to about 18 μm (3 μm anode+12 μm aperture+3μm cathode) providing a 18×18 μm² die. Die dimensions L may be furtherreduced or slightly increased for smaller aperture dimensions D (e.g.,10 μm) or larger aperture dimensions D (e.g., 20 μm). More generally,VCSEL dies 200 according to embodiments herein may achieve a contactarea-to-aperture area ratio of about 0.05 to 30, about 0.1 to 20, about1 to 10, or about 1 to 3, where the contact area refers to the surfacearea of electrical contacts 211 and/or 212 positioned on or adjacent theaperture 210 on the surface S. Also, although illustrated with referenceto contacts 211, 212 and interconnections 213 at particular locationsrelative to the aperture 210, it will be understood that embodimentsdescribed herein are not so limited, and the contacts 211, 212 andinterconnections 213 may be provided at other areas of the VCSEL die 200(e.g., at corners, etc.).

VCSELs 200 in accordance with some embodiments described herein may beconfigured to emit light with greater than about 100 milliwatts (mW) ofpower within about a 1-10 nanosecond (ns) wide pulse width, which may beuseful for LIDAR applications, among others. In some embodiments, morethan 1 Watt peak power output with a 1 ns pulse width at a 10,000:1 dutycycle may be achieved from a single VCSEL element 200, due for instanceto the reduced capacitance (and associated reduction in RLC timeconstants) as compared to some conventional VCSELs. VCSELs 200 asdescribed herein may thus allow for longer laser lifetime (based uponlow laser operating temperatures at high pulsed power), in combinationwith greater than about 200 meter (m) range (based on very high poweremitter and increased detector sensitivity).

FIG. 2C is a plan view illustrating the VCSEL chip 200 in accordancewith some embodiments described herein in comparison to a conventionalVCSEL chip 10. As shown in FIG. 2C, the conventional VCSEL chip 10 mayhave a length L of about 200 μm, to provide sufficient area for theactive region 5 and the top conductive wire bond pad 11, which mayfunction as an n-type or p-type contact. In contrast, VCSEL chips 200 inaccordance with some embodiments described herein may have a length L ofabout 20 μm or less. As electrical connections to the smaller contacts211, 212 are provided by thin-film metallization interconnects 213,VCSEL chips 200 in accordance with some embodiments described hereinrequire no bond pad, such that the optical aperture 210 occupies amajority of the overall surface area of the emitting surface S.

VCSEL chips 200 according to some embodiments of the present inventionmay thus have dimensions that are 1/100^(th) of those of someconventional VCSEL chips 10, allowing for up to one hundred times morepower per area of the emitting surface S, as well as reduced capacitancewhich may substantially reduce the RLC time constants associated withdriving fast pulses into these devices. Such an exponential reduction insize may allow for fabrication of VCSEL arrays including thousands ofclosely-spaced VCSELs 200, some of which are electrically connected inseries (or anode-to-cathode) on a rigid or flexible substrate, which maynot be possible for some conventional closely spaced VCSELs that arefabricated on a shared electrical substrate. For example, as describedin greater detail below, multiple dies 200 in accordance with someembodiments described herein may be assembled and electrically connectedwithin the footprint of the conventional VCSEL chip 10. In someapplications, this size reduction and elimination of the bond pad mayallow for reduction in cost (of up to one hundred times), devicecapacitance, and/or device thermal output, as compared to someconventional VCSEL arrays.

FIG. 3A is a perspective view illustrating a distributed emitter array300 a including laser diodes (illustrated as VCSELs 200) in accordancewith some embodiments described herein. The array 300 a (also referredto herein as a distributed VCSEL array (DVA)) may be assembled on anon-native substrate 307 a, for example, by micro-transfer printing,electrostatic adhesion, or other mass transfer techniques. As usedherein, a non-native substrate (also referred to herein as a targetsubstrate) may refer to a substrate on which the laser diodes 200 arearranged or placed, which differs from a native substrate on which thelaser diodes 200 are grown or otherwise formed (also referred to hereinas a source substrate). The substrate 307 a may be rigid in someembodiments, or may be flexible in other embodiments, and/or may beselected to provide improved thermal characteristics as compared to thesource substrate. For example, in some embodiments the non-nativesubstrate 307 a may be thermally conducting and also electricallyinsulating (or coated with an insulating material, such as an oxide,nitride, polymer, etc.). Electrically conductive thin-film interconnects313 may be formed to electrically connect respective contacts of thelaser diodes 200 in series and/or parallel configurations, and may besimilar to the interconnects 213 described above. This may allow fordynamically adjustable configurations, by controlling operation ofsubsets of the laser diodes 200 electrically connected by the conductivethin-film interconnects 313. In some embodiments, the array 300 a mayinclude wiring 313 between VCSELs 200 that are not connected in parallel(e.g., connections without a shared or common cathode/anode). That is,the electrically conductive thin-film interconnects 313 may providenumerous variations of series/parallel interconnections, as well asadditional circuit elements which may confer good yield (e.g. bypassroutes, fuses, etc.).

The conductive thin-film interconnects 313 may be formed in a parallelprocess, before and/or after providing the laser diodes 200 on thesubstrate 307 a. For example, the conductive thin-film interconnects 313may be formed by patterning an electrically conductive film on thesubstrate 307 a using conventional photolithography techniques, suchthat the laser diodes 200 of the array 300 are free of electricalconnections through the substrate 307 a.

Due to the small dimensions of the laser diodes 200 and the connectionsprovided by the conductive thin-film interconnects 313, a spacing orpitch between two immediately adjacent laser diodes 200 is less thanabout 500 micrometers (μm), or in some embodiments, less than about 200μm, or less than about 150 μm, or less than about 100 μm, or less thanabout 50 μm, without connections to a shared or common cathode/anode.While some monolithic arrays may provide inter-laser diode spacings ofless than about 100 μm, the laser diodes of such arrays may electricallyshare a cathode/anode and may mechanically share a rigid substrate inorder to achieve such close spacings. In contrast, laser diode arrays asdescribed herein (such as the array 300 a) can achieve spacings of lessthan about 150 μm between immediately adjacent, serially-connected laserdiodes 200 (that do not have a common anode or cathode connection), onnon-native substrates (e.g., rigid or flexible substrates) in someembodiments. In addition, as described below with reference to theexamples of FIGS. 6A-6C, some embodiments of the present disclosure mayintegrate other types of devices and/or devices formed from differentmaterials (e.g. power capacitors, FETs, etc.) in-between laser diodes200 at the sub-150 μm spacings described herein.

Also, in some embodiments, a concentration of the laser diodes 200 perarea of the array 300 a may differ at different portions of the array300 a. For example, some LIDAR sensor applications may benefit fromhigher resolution in a central portion of the array (corresponding to aforward direction of travel), but may not require such high resolutionat peripheral regions of the array. As such, a concentration of VCSELs200 at peripheral portions of the array 300 a may be less than aconcentration of VCSELs 200 at a central portion of the array 300 a insome embodiments. This configuration may be of use in applications wherethe substrate is flexible and may be curved or bent in a desired shape,as shown in FIG. 3B.

FIG. 3B is a perspective view illustrating a distributed emitter array300 b including laser diodes 200 on a curved, non-native substrate 307 bin accordance with some embodiments described herein. In someembodiments, the substrate 307 b is formed of a flexible material thatcan be bent to provide curved emitting surface, such that VCSELs 200mounted on a central portion 317 of the substrate 307 b face a forwarddirection, while VCSELs 200 mounted on peripheral portions 317′ of thesubstrate 307 b face oblique directions. As the VCSELs 200 respectivelyemit light in a direction perpendicular to their active regions, theVCSELs 200 mounted on the central portion 317 emit light 309 in theforward direction, while the VCSELs 200 mounted on peripheral portions317′ of the substrate 307 b emit light 309′ in oblique directions,providing a wide field of view. In some embodiment, each VCSEL mayprovide narrow-field illumination (e.g., covering less than about 1degree), and the arrays 300 a, 300 b may include hundreds or thousandsof VCSELs 200 (e.g., an array of 1500 VCSELs, each covering a field ofview of about 0.1 degree, can provide a 150 degree field of view).

The field of view can be tailored or changed as desired from 0 degreesup to about 180 degrees by altering the curvature of the substrate 307b. The curvature of the substrate 307 b may or may not be constantradius, and can thereby be designed or otherwise selected to provide adesired power distribution. For example, the substrate 307 b may definea cylindrical, acylindrical, spherical or aspherical curve whose normalsurfaces provide a desired distribution of relative amounts of power. Insome embodiments, the curvature of the substrate 307 b may bedynamically altered by mechanical or electro-mechanical actuation. Forexample, a mandrel can be used to form the cylindrical or acylindricalshape of the flexible non-native substrate 307 b. The mandrel can alsoserve as a heat sink in some embodiments. Also, as mentioned above, aspatial density or concentration of VCSELs 200 at peripheral portions ofthe array 300 b may be less than a concentration of VCSELs 200 at acentral portion of the array 300 b in some embodiments.

The arrays 300 a and 300 b illustrated in FIGS. 3A and 3B may bescalable based on a desired quantity or resolution of laser diodes 200,allowing for long range and high pulsed power output (on the order ofkilowatts (kW)). The spatial density or distribution of the laser diodes200 on the surfaces of the substrates 307 a and 307 b can be selected toreduce optical power density, providing both long range and eye safetyat a desired wavelength of operation (e.g., about 905 nm for GaAsVCSELs; about 1500 nm for InP VCSELs). A desired optical power densitymay be further achieved by controlling the duty cycle of the signalsapplied to the VCSELs and/or by altering the curvature of the substrate.Also, the separation or spacing between adjacent laser diodes 200 withinthe arrays 300 a and 300 b may be selected to provide thermal managementand improve heat dissipation during operation, depending on thesubstrate material. For example, a spacing between two immediatelyadjacent laser diodes 200 of greater than about 100 μm micrometers (μm)may provide thermal benefits, especially for substrates with limitedthermal conductivity. The arrays 300 a and 300 b as described herein maythereby provide greater reliability, by eliminating wire bonds,providing a fault-tolerant architecture, and/or providing loweroperating temperatures. In further embodiments, self-aligning, low-costbeam forming micro-optics (e.g., ball lens arrays) may be integrated onor into the surface of the arrays 300 a and 300 b.

The compact arrays 300 a and 300 b shown in FIGS. 3A and 3B may befabricated in some embodiments using micro-transfer printing (MTP),electrostatic adhesion, and/or other massively parallel chip handlingtechniques that allow simultaneous assembly and heterogeneousintegration of thousands of micro-scale devices on non-native substratesvia epitaxial liftoff. For example, the arrays of VCSELs 200 can befabricated using micro-transfer printing processes similar to thosedescribed, for example, in U.S. Pat. No. 7,972,875 to Rogers et al.entitled “Optical Systems Fabricated By Printing-Based Assembly,” thedisclosure of which is incorporated by reference herein in its entirety.The arrays of VCSELs 200 can alternatively be fabricated usingelectrostatic adhesion or gripping transfer techniques similar to thosedescribed, for example in U.S. Pat. No. 8,789,573 to Bibl et al.entitled “Micro device transfer head heater assembly and method oftransferring a micro device,” the disclosure of which is incorporated byreference herein in its entirety. In some embodiments, MTP,electrostatic adhesion, and/or other mass transfer techniques may allowfor fabrication of VCSEL or other arrays of laser diodes with the smallinter-device spacings described herein.

FIGS. 4A-4F are perspective views and FIGS. 4A′-4G′ are cross-sectionalviews illustrating an example fabrication process for laser diodes(illustrated as VCSELs 400) in accordance with some embodimentsdescribed herein. The VCSELs 200 described herein may also be fabricatedusing one or more of the processing operations shown in FIGS. 4A-4F insome embodiments. As shown in FIGS. 4A-4F and FIGS. 4A′-4G′, ultra smallVCSELs 400 in accordance with embodiments described herein can be grownon source substrates and assembled on a non-native target substrateusing micro-transfer printing techniques. In particular, in FIGS. 4A and4A′, sacrificial layer 408, a lateral conduction layer 406, a first,n-type distributed Bragg reflector (DBR) layer 401, an active region405, and a second, p-type DBR layer 402 are sequentially formed on asource wafer or substrate 404. Although illustrated with reference to asingle VCSEL 400 to show fabrication, it will be understood that aplurality of VCSELs 400 may be simultaneously fabricated on the sourcewafer 404, with reduced or minimal spacing between adjacent VCSELs 400to increase or maximize the number of VCSELs that may be simultaneouslyfabricated on the wafer 404. Also, it will be understood that aplurality of VCSEL devices may be fabricated on a single die or chipletthat is released from the substrate 404 for printing. Also, the transfertechniques described in greater detail below may allow for reuse of thesource wafer 404 for subsequent fabrication of additional VCSELs.

In some embodiments, the material compositions of the layers 406, 401,405, and 402 may be selected to provide a desired emission wavelengthand emission direction (optical axis). For example, the layers 406, 401,405, and 402 may be gallium arsenide (GaAs)-based or indium phosphide(InP)-based in some embodiments. As illustrated, a lateral conductionlayer 406, an AlGaAs n-type high-reflectivity distributed Braggreflector (DBR), and an active region 405 are sequentially formed on thesource wafer 404. The active region 405 may be formed to includeInAlGaAs strained quantum wells designed to provide light emission overa desired wavelength, and is followed by formation of a p-type DBRoutput mirror 402. A top contact metallization process is performed toform a p-contact (e.g., an anode contact) 411 on the p-type DBR layer402. For example, Ti/Pt/Au ring contacts of different dimensions may bedeposited to form the anode or p-contact 411. An aperture 410 may bedefined within a perimeter of the p-contact 411. In some embodiments, anoxide layer may be provided between the active region 405 and the p-typeDBR layer 402 to define boundaries of the aperture 410. The placementand design of the aperture 410 may be selected to minimize opticallosses and current spreading.

In FIGS. 4B and 4B′, a top mesa etching process is performed to exposethe active region 405 and a top surface of the n-type DBR layer 401, andan oxidation process is performed to oxidize the exposed surfaces,(including the exposed sidewalls of the active region 405), and inparticular to laterally define boundaries of the optical aperture 410.In FIGS. 4C and 4C′, a bottom contact metallization process is performedto expose and form an n-type (e.g., cathode) contact 412 on a surface ofthe lateral conduction layer 406. It will be understood that, in someembodiments, the n-type contact 412 may alternatively be formed on then-type DBR layer 401 to provide the top-side contact. In FIGS. 4D and4D′, an isolation process is performed to define respective lateralconduction layers 406, and an anchor material (e.g., photoresist layer)is deposited and etched to define photoresist anchors 499 and inlets toexpose sacrificial release layer 408 for epitaxial lift-off.

In FIGS. 4E and 4E′, an undercut etching process is performed to removeportions of the sacrificial release layer 408 such that the anchors 499suspend the VCSEL die 400 over the source wafer 404. In someembodiments, the operations of FIGS. 44E and 4E′ may be followed by amicro-transfer printing process, as shown in FIGS. 4F and 4F′, which mayutilize an elastomeric and/or other stamp 490 to break the anchors 499,adhere the VCSEL die 400 (along with multiple other VCSEL dies 400 onthe source wafer 404) to a surface of the stamp 490, and simultaneouslytransfer the multiple VCSEL dies 400 (which have been adhered to thesurface of the stamp) to a non-native target substrate 407 by contactingthe surface of the stamp including the dies 400 thereon with a surfaceof the non-native target substrate 407, as shown in FIG. 4G′. In otherembodiments, the operations of FIG. 4F may be followed by anelectrostatic gripper-based transfer process, which may utilize anelectrostatic transfer head to adhere the VCSEL die 400 (along withmultiple other VCSEL dies 400 on the source wafer 404) to a surface ofthe head using the attraction of opposite charges, and simultaneouslytransfer the VCSEL dies 400 to a non-native target substrate. As aresult of breaking the anchors 499, each VCSEL die 400 may include abroken or fractured tether portion 499 t (e.g., a residual portion ofthe anchor structure 499) protruding from or recessed within an edge orside surface of the die 400 (and/or a corresponding relief feature at aperiphery of the die 400), which may remain upon transfer of the VCSELdies 400 to the non-native substrate 407.

The non-native target substrate may be a rigid or flexible destinationsubstrate for the VCSEL array, or may be a smaller interposer or“chiplet” substrate. Where the target substrate is the destinationsubstrate for the array, an interconnection process may form aconductive thin film layer on the target substrate including theassembled VCSEL dies 400 thereon, and may pattern the conductive thinfilm layer to define thin-film metal interconnects that provide desiredelectrical connections between the VCSEL dies 400. The interconnectionprocess may be performed after the VCSEL dies 400 are assembled on thedestination substrate, or may be performed in a pre-patterning processon the destination substrate before the VCSEL dies 400 are assembledsuch that the electrical connections between the VCSEL dies 400 arerealized upon assembly (with no interconnection processing requiredafter the transfer of the dies 400 onto the substrate). Where the targetsubstrate is a chiplet, the VCSEL dies 400 may be connected in parallelvia the chiplet. The chiplets including the VCSEL dies 400 thereon maythen be assembled (via transfer printing, electrostatic adhesion, orother transfer process) onto a destination substrate for the array,which may be pre- or post-patterned to provide electrical connectionsbetween the chiplets. The thin-film metal interconnects may be definedon and/or around the broken tether portion 499 t protruding from theedge of the die(s) 400 in some embodiments.

Because the VCSELs 400 are completed via epitaxial lift-off and thus areseparated from the substrate, and because of the use of thin filminterconnects, the VCSELs 400 may also be thinner than some conventionalVCSELs which remain connected to their native substrate, such as theVCSEL 10 of FIG. 2C. For example, the VCSEL 400 may have a thickness t(e.g., a combined thickness of the semiconductor stack including thelayers 406, 401, 405, and 402) of about 1 micrometers (μm) to about 20μm.

FIGS. 5A-5C are images of VCSEL arrays 500 in accordance with someembodiments described herein, which were assembled using micro-transferprinting processes. In particular, FIG. 5A illustrates a VCSEL array 500of about 11,000 lasers with an inter-VCSEL spacing of about 200micrometers (μm) or less between adjacent VCSELs 200 after assembly on anon-native substrate 507, with the inset image of FIG. 5B and the imageof 5C illustrating magnified views of portions of the array 500including about 350 lasers and 9 lasers, respectively, in accordancewith some embodiments described herein. Due to the reduction indimensions of the VCSELs described herein, the inter-VCSEL spacingbetween immediately adjacent VCSELs 200 may be less than about 150 μm,or less than about 100 μm or less than about 50 μm on the sourcesubstrate in some embodiments. In some embodiments, the array 500 mayinclude 100 VCSELs or more within a footprint or area of 5 squaremillimeters (mm²) or less.

FIGS. 5D-5E are magnified images illustrating broken tether portions andrelief features of VCSEL structures in accordance with some embodimentsdescribed herein. As shown in FIGS. 5D and 5E, a transfer-printed VCSEL510 (such as one of the VCSELs 200) or other laser diode as describedherein may include one or more residual or broken tether portions 499 tand/or relief features 599 at a periphery thereof. The relief features599 may be patterned or otherwise provided along the periphery of VCSEL510 to partially define the tethers 499 and areas for preferentialfracture of the tethers 499. In the examples of FIGS. 5D-5E, the brokentether portions 499 t and relief features 599 are illustrated as beingpresent along a periphery of the lateral conduction layer (LCL) 506;however, it will be understood that broken tether portions 499 t and/orrelief features 599 may be present in or along a periphery of any of thelayers that may be provided on a non-native substrate bytransfer-printing processes described herein, for example, any of theepitaxially grown layers 406, 405, 401, 402 formed in fabricating theactive region 405 on a source wafer or substrate 404 in the examples ofFIGS. 4A-4F and 4A′-4G′. As such, in some embodiments, the broken tetherportion 499 t may comprise a material and thickness corresponding tothat of the LCL layer 506 (or other layer associated with the activeregion). In further embodiments, to shorten an etch sequence, peripheralor edge portions of the LCL 506 may be partially etched, and as such,the relief pattern 599 of the tether features 499 t may be thinner thanthe LCL 506 (or other layer associated with the active region). Thefracture of the tethers 499 during the “Pick” operation (such as shownin FIG. 4G′) may occur in the resist layer 4991 itself, and the brokentether portions 499 t may comprise a material and thicknesscorresponding to that of the resist layer 4991. The broken tetherportion 499 t may interact with the print adhesive or epoxy, and alsoremains on the fully processed device, even after resist develop and/orresist removal processes. More generally, some laser diode structures inaccordance with embodiments described herein may include at least one ofa broken tether portion 499 t or a relief pattern or feature 599 along aperiphery or edge of the laser diode structure.

Accordingly, some embodiments described herein may use MTP to print andintegrate hundreds or thousands of VCSELs or other surface-emittinglaser diodes into small-footprint light-emitting arrays. MTP may beadvantageous by allowing simultaneous manipulation and wafer-levelassembly of thousands of laser diode devices. In some embodiments, eachof the laser diodes may have aperture dimensions as small as about 1-10μm, thereby reducing the size (and cost) of lasers incorporating suchVCSEL arrays by a factor of up to 100. Other embodiments may includesubstrates with aperture dimensions even smaller than about 1 μm inorder to realize different performance such as modified near and farfield patterns. Still other embodiments may use larger apertures, forexample, about 10-100 μm, in order to realize higher power output perVCSEL device. Also, MTP allows reuse of the source wafer (e.g., GaAs orInP) for growth of new devices after the transfer printing process,further reducing fabrication costs (in some instances, by up to 50%).MTP may also allow heterogeneous integration and interconnection oflaser diodes of different material systems (e.g., GaAs or InP lasers)and/or driver transistors (as discussed below) directly onto siliconintegrated circuits (ICs). Also, source wafers may be used and reused ina cost-effective manner, to fabricate laser diodes (e.g., InP-basedVCSELs) that can provide high power with eye safety, as well as reducedambient noise. As such, MTP may be used in some embodiments to reduceemitter costs, and allow fabrication of high power, high resolutiondistributed VCSEL arrays (DVAs) including multiple hundreds or thousandsof VCSELs.

Also, when provided on flexible or curved substrates, embodimentsdescribed herein can provide DVAs having a wide field of view (FoV), upto 180 degrees horizontal. In some embodiments, the optical powerdispersed via the DVA can be configured for eye safety and efficientheat dissipation. In some embodiments, low-cost, self-aligning, beamforming micro-optics may be integrated within the curved DVA.

FIG. 6A is a perspective view illustrating an example emitter array 600including heterogeneous integration of distributed surface-emittinglaser diodes (illustrated as VCSELs 200) and distributed drivertransistors 610 in accordance with some embodiments described herein. Asused herein, distributed circuit elements may refer to laser diodes,driver transistors, and/or other circuit elements that are assembled invarious desired positions throughout a laser diode array, and such anarray of distributed circuit elements is referred to herein as adistributed array. For example, integration of distributed high powerdriver transistors in a distributed VCSEL array may be advantageous forLIDAR applications. FIG. 6B is schematic view illustrating an equivalentcircuit diagram for the distributed emitter array 600 of FIG. 6A, andFIG. 6C is a cross-sectional view of the distributed emitter array 600taken along line 6C-6C′ of FIG. 6A.

As shown in FIGS. 6A-6C, the array 600 (also referred to herein as aDVA) may be assembled on a non-native substrate 607, for example, bymicro-transfer printing or other techniques. The substrate 607 may berigid in some embodiments, or may be flexible in other embodiments. Thearray 600 further includes integrated driver transistors 610 that areassembled on the substrate 607 adjacent to one or more of the VCSELs200. In some embodiments, the drivers 610 and laser diodes 200 mayinclude different semiconductor materials and/or technologies that haveincompatible fabrication processes. For example, the driver transistors610 may be assembled on the substrate 607 using a micro-transferprinting (MTP) process. In some embodiments, an array including hundredsor thousands of driver transistors 610 may be provided. Electricallyconductive thin-film interconnects 613 may be formed to electricallyconnect respective contacts of the driver transistors 610 and laserdiodes 200 in series and/or parallel configurations. Spacings between adriver transistor 610 and an immediately adjacent laser diode 200 may beless than about 2 millimeters, less than about 1 millimeter, less thanabout 500 micrometers, less than about 150 micrometers (μm), or in someembodiments, less than about 100 μm, or less than about 50 μm, which mayprovide reduced parasitic impedance therebetween (e.g., up to 100 timeslower than where the driver transistor 610 is located off-chip oroff-substrate).

In some embodiments, the array 600 may include wiring 613 between VCSELs200 that are not connected in parallel (e.g., no common cathode/anode).Interconnection designs that do not simply place all elements of thearray in parallel (e.g., without a common anode or cathode connection)may offer the advantage of lowering current requirements for the array,which can reduce inductive losses and increase switching speed. Variedinterconnection designs also provide for the inclusion of other devicesembedded or integrated within the electrically interconnected array(e.g., switches, gates, FETs, capacitors, etc.) as well as structureswhich enable fault tolerance in the manufacture of the array (e.g.fuses, bypass circuits, etc.) and thus confer yield advantages. Forexample, as illustrated in FIG. 6B, the array 600 includes a pluralityof strings of VCSELs 200 that are electrically connected in series (oranode-to-cathode) to define columns (or other subsets or sub-arrays) ofthe array 600. The array 600 further includes an array of drivertransistors 610, with each driver 610 electrically connected in serieswith a respective string of serially- or anode-to-cathode-connectedVCSELs 200.

The conductive thin-film interconnects 613 may be formed in a parallelprocess after providing the laser diodes 200 and driver transistors 610on the substrate 607, for example by patterning an electricallyconductive film using conventional photolithography techniques. As such,the driver transistors 610 and laser diodes 200 of the array 600 arefree of wire bonds and/or electrical connections through the substrate607. Due to the smaller dimensions of the laser diodes 200 and thedriver transistors 610 and the degree of accuracy of the assemblytechniques described herein, a spacing between immediately adjacentlaser diodes 200 and/or driver transistors 610 may be less than about150 micrometers (μm), or in some embodiments, less than about 100 μm orless than about 50 μm. Integrating the driver transistors 610 on thesubstrate 607 in close proximity to the VCSELs 200 (for example, atdistances less than about 2 millimeters, less than about 1 millimeter,less than about 500 micrometers, less than about 150 micrometers (μm),or in some embodiments, less than about 100 μm, or less than about 50 μmfrom a nearest VCSEL 200) may thus shorten the electrical connections613 between elements, thereby reducing parasitic resistance, inductance,and capacitance, and allowing for faster switching response.

In the example of FIGS. 6A-6C, the driver transistors 610 are arrangedin an array such that each driver transistor 610 is connected in serieswith a column (or other subset or sub-array) of serially-connected (orotherwise anode-to-cathode—connected) VCSELs 200, allowing forindividual control of respective columns/strings of VCSELs 200. However,it will be understood that embodiments described herein are not limitedto such a connection configuration. To the contrary, integrating thedriver transistors 610 in close proximity to the VCSELs 200 may alsoallow for greater flexibility in wiring configurations (e.g., in seriesand/or parallel), which may be used to control current and/or increaseor maximize performance. For example, fewer or more driver transistors610 may be provided (e.g., drivers for control of rows ofserially-connected VCSELs 200 as well as columns) for finer control ofrespective VCSELs or groups of VCSELs and/or output power. Anotherexample would be the addition of capacitors or similar electricalstorage devices close to the elements of the array for faster pulsegeneration, for example, on the order of sub-nanosecond (ns), incontrast to some conventional designs that may be on the order of about1-10 ns or more. Likewise, although illustrated as a planar array 600,the substrate 607 may be flexible in some embodiments; thus, the array600 may be bent to provide a desired curvature, similar to the array 300b of FIG. 3B.

As similarly discussed above with reference to the arrays 300 a and 300b, the array 600 may be scalable based on a desired quantity orresolution of laser diodes 200, allowing for long range and high pulsedpower output (on the order of kilowatts (kW)). The distribution of thelaser diodes 200 on the surfaces of the substrate 607 can be selectedand/or the operation of the laser diodes can be dynamically adjusted orotherwise controlled (via the transistors 610) to reduce optical powerdensity, providing both long range and eye safety at a desiredwavelength of operation (e.g., about 905 nm for GaAs VCSELs; about 1500nm for InP VCSELs). Also, the spacing between elements 200 and/or 610may be selected to provide thermal management and improve heatdissipation during operation. Arrays 600 as described herein may therebyprovide improved reliability, by eliminating wire bonds, providing afault-tolerant architecture, and/or providing lower operatingtemperatures. In further embodiments, self-aligning, low-cost beamforming micro-optics (e.g., ball lens arrays) may be integrated on orinto the surface of the array 607.

FIG. 7A is a perspective view illustrating a LIDAR device 700 aincluding surface-emitting laser diodes (such as the VCSELs 200) inaccordance with embodiments described herein, illustrated relative to apencil for scale. FIG. 7C is a perspective view illustrating analternative LIDAR device 700 c in accordance with embodiments describedherein. In particular, FIGS. 7A and 7C illustrate a distributedvertical-cavity-surface-emitting laser (VCSEL) array-based, solid-stateFlash LIDAR device 700 a, 700 c. The LIDAR device 700 a, 700 c isillustrated with reference to a curved array 720, such as the curvedarray 300 b of FIG. 3B, but it will be understood that the LIDAR device700 a, 700 c is not so limited, and may alternatively implement thearray 300 a of FIG. 3A, the array 600 of FIGS. 6A-6C, and/or otherarrays of laser diodes 200 that provide features described herein. Suchfeatures of the device 700 a, 700 c may include, but are not limited to,broad field of view (in particular embodiments, about 0=120° horizontalby 4=10° vertical, or broader); long range (in some instances, greaterthan about 200 m); high resolution (in particular embodiments, about0.1° horizontal and vertical) compact size defined by reduced dimensions(in particular embodiments, about 110×40×40 mm); high power (inparticular embodiments, about 10,000 w peak, pulsed); and eye safety (inparticular embodiments, dispersed optical power can support eye safe,high power, 905 nm (e.g., GaAs) and/or about 1500 nm (e.g., InP)emitters).

FIG. 7B is an exploded view 700 b illustrating components of the LIDARdevice 700 a of FIG. 7A. As shown in FIG. 7B, the device housing orenclosure 701 includes a connector 702 for electrical connection to apower source and/or other external devices. The enclosure 701 is sizedto house a light emitter array 720, a light detector array 730,electronic circuitry 760, detector optics 740 (which may include one ormore lenses and/or optical filters), and a lens holder 770. Atransparent cover 780 is provided to protect the emitter array 720 anddetector optics 740, and may include beam shaping and/or filteringoptics in some embodiments.

The light emitter array 720 may be a pulsed laser array, such as any ofthe VCSEL arrays 300 a, 300 b, 600 described herein. As such, the lightemitter array 720 may include a large quantity (e.g., hundreds or eventhousands) of distributed, ultra small laser diodes 200, which arecollectively configured to provide very high levels of power (byexploiting benefits of the large number of very small devices). Using alarge number of small devices rather than a small number of largedevices allows devices that are very fast, low power and that operate ata low temperature to be integrated in an optimal configuration (withother devices, such as transistors, capacitors, etc.) to provideperformance not as easily obtained by a small number of larger laserdevices. As described herein the laser diodes 200 may be transferprinted simultaneously onto a non-native curved or flexible substrate insome embodiments. Beam shaping optics that are configured to projecthigh aspect ratio illumination from the light emitter array 720 onto atarget plane may also be provided on or adjacent the light emitter array720.

The light detector array 730 may include one or more optical detectordevices, such as pin, pinFET, linear avalanche photodiode (APD), siliconphotomultiplier (SPM), and/or single photon avalanche diode (SPAD)devices, which are formed from materials or otherwise configured todetect the light emitted by the light emitter array 720. The lightdetector array 730 may include a quantity of optical detector devicesthat are sufficient to achieve a desired sensitivity, fill factor, andresolution. In some embodiments, the light detector array 730 may befabricated using micro-transfer printing processes as described herein.The detector optics 740 may be configured to collect high aspect ratioecho and focus target images onto focal plane of the light detectorarray 730, and may be held on or adjacent the light detector array 730by the lens holder 770.

The electronic circuitry 760 integrates the above and other componentsto provide multiple return LIDAR point cloud data to data analysis. Moreparticularly, the electronic circuitry 760 is configured to controloperation of the light emitter array 720 and the light detector array730 to output filtered, high-quality data, such as 3D point cloud data,to one or more external devices via the connector 702. The externaldevices may be configured to exploit proprietary and/or open source 3Dpoint cloud ecosystem and object classification libraries for analysisof the data provided by the LIDAR device 700 a, 700 c. For example, suchexternal devices may include devices configured for applicationsincluding but not limited to autonomous vehicles, ADAS, UAVs, industrialautomation, robotics, biometrics, modeling, augmented and virtualreality, 3D mapping, and/or security.

FIG. 8 is a block diagram illustrating an example system 800 for a LIDARdevice, such as the LIDAR device 700 a, 700 b, 700 c of FIGS. 7A-7C, inaccordance with some embodiments described herein. As shown in FIG. 8,the system 800 integrates multiple electrically coupled integratedcircuit elements to provide the LIDAR device functionality describedherein. In particular, the system 800 includes a processor 805 that iscoupled to a memory device 810, an illumination circuit 820, and adetection circuit 830. The memory device 810 stores computer readableprogram code therein, which, when executed by the processor, operatesthe illumination circuit 820 and the detection circuit 830 to collect,process, and output data, such as 3D point cloud data, indicative of oneor more targets in the operating environment. The system 800 may furtherinclude a thermistor 842 and associated temperature compensation circuit843, as well as a power management circuit 841 that is configured toregulate voltage or power to the system 800.

The illumination circuit 820 includes an array of surface-emitting laserdiodes 200, driver transistor(s) 610, and associated circuit elements611, electrically connected in any of various configurations. In someembodiments, the illumination circuit 820 may be a laser array includingrows and/or columns of VCSELs 200, such as any of the VCSEL arrays 300a, 300 b, 600 described herein. Operation of the illumination circuit820 to emit light pulses 809 may be controlled by the processor 805 viaa modulation and timing circuit 815 to generate a pulsed light output809. Beam-shaping and/or focusing optics may also be included in oradjacent the array of laser diodes 200 to shape and/or direct the lightpulses 809.

The detection circuit 830 may include a time-of-flight (ToF) detector851 coupled to a ToF controller 852. The ToF detector 851 may includeone or more optical detector devices, such as an array of pin, pinFET,linear avalanche photodiode (APD), silicon photomultiplier (SPM), and/orsingle photon avalanche diode (SPAD) devices. The ToF controller 852 maydetermine the distance to a target by measuring the round trip(“time-of-flight”) of a laser pulse 809′ reflected by the target andreceived at the ToF detector 851. In some embodiments, the reflectedlaser pulse 809′ may be filtered by an optical filter 840, such as abandpass filter, prior to detection by the ToF detector 851. The outputof the detection block 830 may be processed to suppress ambient light,and then provided to the processor 805, which may perform furtherprocessing and/or filtering (via signal processor discriminator filter817, and may provide the filtered output data (for example, 3D pointcloud data) for data analysis. The data analysis may include framefiltering and/or image processing. In some embodiments, the dataanalysis may be performed by an external device, for example, anautonomous vehicle intelligence system.

FIG. 9 is a cross-sectional view illustrating an example laser diodearray 900 including edge-emitting laser diodes 910 in accordance withfurther embodiments described herein. As shown in FIG. 9, a laser diode910 includes an active region 905 (which may include one or more quantumwells) for generation and emission of coherent light 909. The activeregion 905 is provided between p-type and n-type layers 901 and 902,with contacts 912 and 911 thereon, respectively. A diffraction gratinglayer may be included to provide feedback for lasing. The optical cavityaxis of the laser diode 910 is oriented perpendicular to the directionof current flow, defining an edge-emitting device, so that the radiation909 emerges from the edge of the device 910 rather than from a topsurface thereof. The devices 910 may be assembled on a non-nativesubstrate 907, for example, by micro-transfer printing, electrostaticadhesion, or other mass transfer techniques. Respective mirror elements(illustrated as micro-steering mirrors 913) may also be assembled on thesubstrate 907 (for example, by micro-transfer printing, electrostaticadhesion, or other mass transfer techniques), and oriented relative tothe optical cavity axis of a laser diode 910 that is to be providedadjacent thereto, such that the radiation 909 from the laser diode 910is reflected and ultimately emitted in a direction perpendicular to thesubstrate 907.

The substrate 907 may be rigid in some embodiments, or may be flexiblein other embodiments, and electrically conductive thin-filminterconnects may be formed to electrically connect respective contactsof the laser diodes 910 in series and/or parallel configurations, atspacings similar to those described with reference to the arrays 300 a,300 b, and/or 600 herein. Likewise, as described above with reference tothe examples of FIGS. 6A-6C, the array 900 may include other types ofdevices and/or devices formed from different materials (e.g., powercapacitors, FETs, micro-lens arrays, etc.) integrated with the laserdiodes 910 on the substrate 907 at the spacings described herein.

The present invention has been described above with reference to theaccompanying drawings, in which embodiments of the invention are shown.However, this invention should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout.

It will be understood that when an element is referred to as being “on,”“connected,” or “coupled” to another element, it can be directly on,connected, or coupled to the other element, or intervening elements maybe present. In contrast, when an element is referred to as being“directly on,” “directly connected,” or “directly coupled” to anotherelement, there are no intervening elements present.

It will also be understood that, although the terms first, second, etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The exemplary term“lower”, can therefore, encompasses both an orientation of “lower” and“upper,” depending of the particular orientation of the figure.Similarly, if the device in one of the figures is turned over, elementsdescribed as “below” or “beneath” other elements would then be oriented“above” the other elements. The exemplary terms “below” or “beneath”can, therefore, encompass both an orientation of above and below.

The terminology used in the description of the invention herein is forthe purpose of describing particular embodiments only and is notintended to be limiting of the invention. As used in the description ofthe invention and the appended claims, the singular forms “a”, “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will also be understood that theterm “and/or” as used herein refers to and encompasses any and allpossible combinations of one or more of the associated listed items. Itwill be further understood that the terms “include,” “including,”“comprises,” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Embodiments of the invention are described herein with reference toillustrations that are schematic illustrations of idealized embodiments(and intermediate structures) of the invention. As such, variations fromthe shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,the regions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the actual shape of a region of adevice and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms used in disclosing embodiments ofthe invention, including technical and scientific terms, have the samemeaning as commonly understood by one of ordinary skill in the art towhich this invention belongs, and are not necessarily limited to thespecific definitions known at the time of the present invention beingdescribed. Accordingly, these terms can include equivalent terms thatare created after such time. It will be further understood that terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe present specification and in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein. All publications, patent applications,patents, and other references mentioned herein are incorporated byreference in their entireties.

Many different embodiments have been disclosed herein, in connectionwith the above description and the drawings. It will be understood thatit would be unduly repetitious and obfuscating to literally describe andillustrate every combination and subcombination of these embodiments.Accordingly, the present specification, including the drawings, shall beconstrued to constitute a complete written description of allcombinations and subcombinations of the embodiments of the presentinvention described herein, and of the manner and process of making andusing them, and shall support claims to any such combination orsubcombination.

Although the invention has been described herein with reference tovarious embodiments, it will be appreciated that further variations andmodifications may be made within the scope and spirit of the principlesof the invention. Although specific terms are employed, they are used ina generic and descriptive sense only and not for purposes of limitation,the scope of embodiments of the present invention being set forth in thefollowing claims.

That which is claimed:
 1. A laser diode, comprising: a semiconductorstructure comprising an n-type layer, an active region, and a p-typelayer, one of the n-type and p-type layers comprising a lasing aperturehaving an optical axis oriented perpendicular to a surface of the activeregion between the n-type and p-type layers; and first and secondcontacts electrically connected to the n-type and p-type layers,respectively, wherein each of the first and second contacts is smallerthan the lasing aperture in at least one dimension in plan view.
 2. Thelaser diode of claim 1, wherein a respective contact area of each of thefirst and second contacts in plan view is smaller than an aperture areaof the lasing aperture.
 3. The laser diode of claim 1, wherein the laserdiode is free of wire bond pads that are electrically connected to thefirst and second contacts.
 4. The laser diode of claim 1, furthercomprising: a lateral conduction layer comprising a surface includingthe semiconductor structure thereon, wherein the lateral conductionlayer is distinct from the n-type and p-type layers, and wherein one ofthe first and second contacts is on the surface of the lateralconduction layer adjacent the semiconductor structure and outside of then-type and p-type layers.
 5. The laser diode of claim 4, wherein thelaser diode is freed of a native substrate thereof.
 6. The laser diodeof claim 5, further comprising: a non-native substrate including thelaser diode on a surface thereof, wherein the non-native substratecomprises electrically insulating and/or thermally conductingcharacteristics, and wherein the laser diode is free of electricalconnections through the non-native substrate.
 7. The laser diode ofclaim 6, wherein the n-type and p-type layers comprise first and secondBragg reflector layers, respectively, and wherein the laser diodecomprises a vertical cavity surface emitting laser (VCSEL).
 8. A LightDetection and Ranging (LIDAR) emitter, comprising: a plurality of laserdiodes arranged in an array on a surface of a non-native substrate,wherein each of the laser diodes comprises: a semiconductor structurecomprising an n-type layer, an active region, and a p-type layer, one ofthe n-type and p-type layers comprising a lasing aperture having anoptical axis oriented perpendicular to a surface of the active regionbetween the n-type and p-type layers; and first and second contactselectrically connected to the n-type and p-type layers, respectively,wherein the first and second contacts are smaller than the lasingaperture in at least one dimension in plan view.
 9. The LIDAR emitter ofclaim 8, wherein the first and second contacts of each of the laserdiodes comprise anode and cathode contacts, respectively, and furthercomprising: electrically conductive thin-film interconnects thatelectrically connect the anode and cathode contacts of respectivesubsets of the plurality of laser diodes anode-to-cathode.
 10. The LIDARemitter of claim 9, further comprising: a plurality of drivertransistors, wherein the respective subsets of the plurality of laserdiodes are electrically connected in series with respective drivertransistors of the plurality of driver transistors, and wherein therespective driver transistors are configured to control operation of therespective subsets of the plurality of laser diodes independent of oneanother.
 11. The LIDAR emitter of claim 10, wherein the respectivesubsets of the plurality of laser diodes define rows or columns of thearray, and wherein the respective driver transistors are configured tooperate the rows or columns at different output power levels.
 12. TheLIDAR emitter of claim 11, wherein a concentration of the plurality oflaser diodes at a first portion of the array is less than aconcentration of the plurality of laser diodes at a second portion ofthe array.
 13. The LIDAR emitter of claim 8, wherein the plurality oflaser diodes are free of a native substrate thereof.
 14. A method offabricating a laser diode, the method comprising: separating asemiconductor structure comprising an n-type layer, an active region,and a p-type layer from a native substrate thereof; and providing firstand second contacts electrically connected to the n-type and p-typelayers, respectively, wherein one of the n-type and p-type layerscomprises a lasing aperture having an optical axis orientedperpendicular to a surface of the active region between the n-type andp-type layers, and wherein each of the first and second contacts issmaller than the lasing aperture in at least one dimension in plan view.15. The method of claim 14, wherein a respective contact area of each ofthe first and second contacts in plan view is smaller than an aperturearea of the lasing aperture.
 16. The method of claim 14, wherein thelaser diode is free of wire bond pads that are electrically connected tothe first and second contacts.
 17. The method of claim 14, furthercomprising: forming the semiconductor structure on a surface of alateral conduction layer, wherein the lateral conduction layer isdistinct from the n-type and p-type layers, and wherein one of the firstand second contacts is on the surface of the lateral conduction layeradjacent the semiconductor structure and outside of the n-type andp-type layers.
 18. The method of claim 17, further comprising: providingthe laser diode on a surface of a non-native substrate, wherein thenon-native substrate comprises electrically insulating and/or thermallyconducting characteristics, and wherein the laser diode is free ofelectrical connections through the non-native substrate.
 19. The methodof claim 18, wherein the first and second contacts comprise anode andcathode contacts, respectively, and further comprising: formingelectrically conductive thin-film interconnects on the non-nativesubstrate that electrically connect the anode and cathode contacts ofthe laser diode to cathode and anode contacts, respectively, of adjacentlaser diodes on the surface of the non-native substrate.
 20. The methodof claim 18, wherein the n-type and p-type layers comprise first andsecond Bragg reflector layers, respectively, and wherein the laser diodecomprises a vertical cavity surface emitting laser (VCSEL).